Biasing JFETs to Achieve Zero Drift

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Table of Contents
  1. Introduction
  2. Analysis
  3. Conclusions

Introduction

For certain applications JFETs allow a simple means to achieve near-uniform performance over wide-ranging temperatures. The principle of temperature effect on a silicon JFET affects the channel conductivity \mathsf{\sigma} and the gate-to-channel junction barrier potential \mathsf{\Psi}. As the temperature rises, both \mathsf{\sigma} and \mathsf{\Psi} decrease. This paper analyzes this effect and identifies how a user may apply the principle to achieve near zero temperature-coefficient performance.

Analysis

The operating drain current, transconductance, and channel resistance are dramatically affected by temperature. As the temperature increases the movement (mobility) of majority carriers within the channel is inhibited. For both N-type and P-type silicon, the variation of conductivity generally falls between 0.6\%/\textsf{\degree C} and 0.8\%/\textsf{\degree C}.

The second factor affected by temperature that lends to this analysis is the change attributed to the gate-to-channel depletion region. Any reverse-biased pin junction exhibits a barrier potential depletion width that decreases with increasing temperature. As a consequence, with rising temperature, this decreasing barrier potential appears as a positive temperature coefficient of drain current. The gate-to-channel junction of a JFET exhibits exactly the same temperature coefficient as does the silicon junction bipolar transistor: -2.2 \textsf{mV} / \textsf{\degree C}.

As would be expected as channel conductance decreases, the drain current also decreases. But, as the gate-to-channel barrier potential decreases, the drain current increases. Obviously for the JFET to exhibit zero drift over temperature, the effects of decreasing channel conductance and a decreasing barrier potential must cancel.

Cobbold1 offers the following derivations that allows us to resolve how to achieve the desired zero temperature coefficient.

With a JFET operating in the saturation region, we can define drain current I_D by, 

\begin{equation} \tag{1} I_D = I^{\prime}_D(\Psi,\sigma) \end{equation}

which, on differentiation yields,

\begin{equation} \tag{2} \frac{dI_D}{dT} = \frac{\delta I^{\prime}_D d \Psi}{\sigma \Psi \space dT} + \frac{\sigma I^{\prime}_D d \sigma}{\delta \sigma \space \sigma T} \end{equation}

However, \Large{\frac{\delta I^{\prime}_D}{\delta \Psi} = g^{\prime}_M} when \Large{I_D \propto \sigma} so Equation (2) becomes,

\begin{equation} \tag{3} \frac{dI^{\prime}_D}{dT} = g^{\prime}_M \frac{d \Psi}{dT} + \frac{I^{\prime}_D d \sigma}{\sigma dT} \end{equation}

Substituting 0.7\textsf{\%} for d \sigma / d T and 2.2 \textsf{mV / \degree C} for d \Psi / d T into Equation 3, the condition for zero-temperature coefficients becomes,

\begin{equation} \tag{4} \frac{I^{\prime}_{DZ}}{g^{\prime}_{MZ}} = 0.315 \space \textsf{volts} \end{equation}

This value is close to that observed in practice where the range usually lies within the range 0.29 \textsf{to} 0.33.

Taking Shockley’s power law equation for double-diffused FETs,

\begin{equation} \tag{5} I_D = I_{DSS} \left(1 - \frac{V_{GS}}{V_{GS(OFF)}}\right)^2 \end{equation}

and the equation for transconductance,

\begin{equation} \tag{6} g_{fs} = 2 \frac{I_{DSS}}{V_{GS(OFF)}} \left(1 - \frac{I_{DSS}}{V_{GS(OFF)}} \right) \end{equation}

We divide Equation 5 by Equation 6; then substituting into Equation 4, we arrive at,

\begin{equation} \tag{7} V_{GS(OFF)} - V_{GS} = 0.63 \space \textsf{volts} \end{equation}

This equation identifies that value of V_{GS} that will give zero drift when the gate-source cut-off voltage is known. We see that for a JFET with a gate-source cut-off voltage of 0.63 \textsf{V}, zero drift will occur at V_{GS} = 0 \textsf{V} when I_D = I_{DSS}.

Since \lvert V_{GS(OFF)} \rvert normally lies within the range 1.0 \textsf{V} < \lvert V_{GS(OFF)} \rvert < 5.0 \textsf{V} we see from Equation 7 that the condition for zero temperature coefficient occurs when V_{GS} is close to the gate-source cut-off voltage.

With the JFET operating at zero drift,

\begin{equation} \tag{8} I_{DZ} = I_{DSS} \left(\frac{0.63}{V_{GS(OFF)}}\right)^2 \end{equation}
\begin{equation} \tag{9} g_{MZ} = g^{\prime}_{FS} \left(\frac{0.63}{V_{GS(OFF)}}\right) \end{equation}

Should the JFET under consideration for operation at zero temperature-coefficient have a high V_{GS(OFF)}, its operating drain current I_D will be considerably less than its saturation drain current I_{DSS}. Likewise, for most JFETs the resulting transconductance may be too low to be practical.

Operating at drain currents other than I_{DZ} will result in a drift in V^2_{GS},
\begin{equation} \tag{10} V_{GSDRIFT} = 2.2 \textsf{mV / \degree C} \left(1 - \sqrt{\frac{I_D}{I_{DZ}}}\right) \end{equation}

Conclusions

The values of I_{DZ} and g_{MZ} are proportional to the size of the JFET as defined by its geometry. For the 2N4117/A family we might anticipate an I_{DZ} of 40 – 50 \mu \textsf{A}, with an associated g_{MZ} \space \textsf{of} \space \mu \textsf{S}; for the 2N4338 family an I_{DZ} \space \textsf{of} \space 300 \mu \textsf{A} and a g_{MZ} \space \textsf{of} \space 500 \mu \textsf{S}; and for the 2N4393 series an I_{DZ} \space \textsf{closer to} \space 3 \textsf{mA with a} \space g_{MZ} \space \textsf{in the area of} \space 5 \textsf{mS}.

When operating a JFET below its zero-temperature coefficient, as the temperature rises both drain current and transconductance also rise. Above the JFET’s temperature-coefficient the opposite holds true.

  1. Richard S. C. Cobbold, Theory and applications of Field-Effect Transistors, ©1970 John Wiley & Sons, §3.7.2 “Effects of Temperature on the Channel,” pp. 121-128.
  2. Designing With Field-Effect Transistors, 2nd ed., revised by Ed Oxner, ©1990 McGraw-Hill, Inc.