P Channel vs N Channel JFET: Explained

What is a JFET?

The Junction Field Effect Transistor (JFET) is a unijunction, depletion mode device that can use a voltage applied to a gate with very low leakage to vary channel current with high linearity. Featuring low noise and high radiation tolerance, JFETs are excellent transistors for different applications where precision high-gain amplification is required.

Figure 1 – An InterFET JFET in a TO-72 package

JFETs are available as N-type or P-type devices, which operate under opposite applied voltage conditions. JFETs are fabricated with the substrate of the device serving as the gate, with the channel fabricated as a layer on top of the substrate. A N-type JFET has a substrate of a semiconductor doped as P-type with N-type doping applied to the channel region, and a P-type JFET consists of a N-type substrate with a P-type channel.

representation of n-type jfet
Figure 2 – A simple representation of N-type and P-type JFETs

JFETs operate by a similar mechanism to that of a reverse biased PN-junction, where when a diode is subjected to a positive potential difference from the N-type area to the P-type area, a depletion region will form, and no significant amount of current will be conducted between the two terminals excluding a very small leakage current.

representation of a forward conducting diode
Figure 3 – A simple representation of diode biasing

This property is utilized in JFETs as a means of constricting the channel to reduce the current conducting from the drain to the source, where in N-type JFETs if a positive voltage is applied across the Drain to the Source (VDS≥0)(VDS​≥0), and a voltage less than or equal to zero is applied across the Gate to the Source (VGS≤0)(VGS​≤0), the depletion region created at the junction will be adjusting the positive Drain current (ID≥0)(ID​≥0). Conversely for a P-type JFET, if a negative voltage is applied across the Drain to the Source (VDS≤0)(VDS​≤0), and a voltage greater than or equal to zero is applied across the Gate to the Source (VGS≥0)(VGS​≥0), the depletion region will vary the negative Drain current (ID≤0)(ID​≤0). Figure 4 shows a comparison between a N-type JFET that is fully conducting (VGS=0)(VGS​=0) and a partially conducting one (VGS(OFF)<VGS<0)(VGS(OFF)​<VGS​<0).

unbiased gate, fully conducting
Figure 4 – A simple representation of JFET biasing and conduction

This behavior is a key function for JFETs since the current conducted through the channel can be linearly controlled by adjusting the applied Gate to Source voltage (VGS)(VGS​). Furthermore, at the lower end of a device’s possible Drain to Source voltage (VDS)(VDS​) range, the device will be within its Ohmic region, where the Drain current can be linearly varied by both the VDS and VGSVDS​ and VGS​. This property alone allows JFETs to serve a variety of purposes, acting as simple amplifiers or Voltage Controlled Resistors (VCRs). Figure 5 shows the linear relation of the IDID​ to the applied VGSVGS​, particularly at VGSVGS​ values closer to zero.

Figure 5 – N-type JFET gate to source voltage sweep (N0450SL)

The impact of VDSVDS​ and VGSVGS​ on IDID​ is a crucial characteristic to take for JFETs, which is often taken and depicted as an ID–VDSID​–VDS​ sweep. Figure 6 shows an example of this kind of sweep with a N-type JFET (NJF) and a P-type JFET (PJF) using a J109 N-type JFET and an equivalent P-type JFET. Note how in the Ohmic region, the IDID​ is linear to the applied VDSVDS​ and is linear to the applied VGSVGS​, whereas in the Saturation region, the IDID​ is only linear to the VGSVGS​.

Figure 6 – Comparison of N-type and P-type JFET Drain to Source Voltage sweeps (N0450SL)

Two key parameters of JFETs are the Drain Current Cutoff Voltage (VGS(OFF))(VGS(OFF)​) and the Drain Saturation Current (IDSS)(IDSS​). The Drain Current Cutoff Voltage is the applied gate voltage required to ideally stop all current traveling through a JFET, typically in its Saturation region. The current never completely shuts off, so VGS(OFF)VGS(OFF)​ is measured as the VGSVGS​ required to set the drain current to below some very small value, with preferences ranging from picoamps to microamps. Figure 7 shows a simple representation of the VGS(OFF)VGS(OFF)​ behavior. The Drain Saturation Current is the drain current measured at a prescribed VDSVDS​ in the device’s saturation region with VGS=0VVGS​=0V.

Figure 7 – Channel Conduction Off Diagram