Biasing JFETs to Achieve Zero Drift

Table of Contents

1. Introduction
2. Analysis
3. Conclusions

Introduction

For certain applications JFETs allow a simple means to achieve near-uniform performance over wide-ranging temperatures. The principle of temperature effect on a silicon JFET affects the channel conductivity $\mathsf{\sigma }$σ and the gate-to-channel junction barrier potential $\mathsf{\Psi }$Ψ. As the temperature rises, both $\mathsf{\sigma }$σ and $\mathsf{\Psi }$Ψ decrease. This paper analyzes this effect and identifies how a user may apply the principle to achieve near zero temperature-coefficient performance.

Analysis

The operating drain current, transconductance, and channel resistance are dramatically affected by temperature. As the temperature increases the movement (mobility) of majority carriers within the channel is inhibited. For both N-type and P-type silicon, the variation of conductivity generally falls between $0.6\mathrm{\%}\mathrm{/}\mathsf{\text{°C}}$0.6%/°C and $0.8\mathrm{\%}\mathrm{/}\mathsf{\text{°C}}$0.8%/°C.

The second factor affected by temperature that lends to this analysis is the change attributed to the gate-to-channel depletion region. Any reverse-biased pin junction exhibits a barrier potential depletion width that decreases with increasing temperature. As a consequence, with rising temperature, this decreasing barrier potential appears as a positive temperature coefficient of drain current. The gate-to-channel junction of a JFET exhibits exactly the same temperature coefficient as does the silicon junction bipolar transistor: $-2.2\mathsf{\text{mV}}\mathrm{/}\mathsf{\text{°C}}$−2.2mV/°C.

As would be expected as channel conductance decreases, the drain current also decreases. But, as the gate-to-channel barrier potential decreases, the drain current increases. Obviously for the JFET to exhibit zero drift over temperature, the effects of decreasing channel conductance and a decreasing barrier potential must cancel.

Cobbold¹ offers the following derivations that allows us to resolve how to achieve the desired zero temperature coefficient.

With a JFET operating in the saturation region, we can define drain current $I_D$ID​ by, 

$$\begin{array}{cccc}& {\displaystyle I_D=I_D^{\mathrm{\prime }}(\mathrm{\Psi },\sigma )}& & \end{array}$$ID​=ID′​(Ψ,σ)​(1)​

which, on differentiation yields,

$$\begin{array}{cccc}& {\displaystyle \frac{d{I}_D}{dT}=\frac{\delta I_D^{\mathrm{\prime }}d\mathrm{\Psi }}{\sigma \mathrm{\Psi }dT}+\frac{\sigma I_D^{\mathrm{\prime }}d\sigma }{\delta \sigma \sigma T}}& & \end{array}$$dTdID​​=σΨ dTδID′​dΨ​+δσ σTσID′​dσ​​(2)​

However, $\frac{\delta I_D^{\mathrm{\prime }}}{\delta \mathrm{\Psi }}=g_M^{\mathrm{\prime }}$δΨδID′​​=gM′​ when $I_D\propto \sigma$ID​∝σ so Equation (2) becomes,

$$\begin{array}{cccc}& {\displaystyle \frac{d{I}_D^{\mathrm{\prime }}}{dT}=g_M^{\mathrm{\prime }}\frac{d\mathrm{\Psi }}{dT}+\frac{I_D^{\mathrm{\prime }}d\sigma }{\sigma dT}}& & \end{array}$$dTdID′​​=gM′​dTdΨ​+σdTID′​dσ​​(3)​

Substituting $0.7\mathsf{\text{\%}}$0.7% for $d\sigma \mathrm{/}dT$dσ/dT and $2.2\mathsf{\text{mV}}\mathsf{\text{/}}\mathsf{\text{°C}}$2.2mV / °C for $d\mathrm{\Psi }\mathrm{/}dT$dΨ/dT into Equation 3, the condition for zero-temperature coefficients becomes,

$$\begin{array}{cccc}& {\displaystyle \frac{I_{DZ}^{\mathrm{\prime }}}{g_{MZ}^{\mathrm{\prime }}}=0.315\mathsf{\text{volts}}}& & \end{array}$$gMZ′​IDZ′​​=0.315 volts​(4)​

This value is close to that observed in practice where the range usually lies within the range $0.29\mathsf{\text{to}}0.33$0.29to0.33.

Taking Shockley’s power law equation for double-diffused FETs,

$$\begin{array}{cccc}& {\displaystyle I_D=I_{DSS}{(1-\frac{V_{GS}}{V_{GS(OFF)}})}^2}& & \end{array}$$ID​=IDSS​(1−VGS(OFF)​VGS​​)2​(5)​

and the equation for transconductance,

$$\begin{array}{cccc}& {\displaystyle g_{fs}=2\frac{I_{DSS}}{V_{GS(OFF)}}(1-\frac{I_{DSS}}{V_{GS(OFF)}})}& & \end{array}$$gfs​=2VGS(OFF)​IDSS​​(1−VGS(OFF)​IDSS​​)​(6)​

We divide Equation 5 by Equation 6; then substituting into Equation 4, we arrive at,

$$\begin{array}{cccc}& {\displaystyle V_{GS(OFF)}-V_{GS}=0.63\mathsf{\text{volts}}}& & \end{array}$$VGS(OFF)​−VGS​=0.63 volts​(7)​

This equation identifies that value of $V_{GS}$VGS​ that will give zero drift when the gate-source cut-off voltage is known. We see that for a JFET with a gate-source cut-off voltage of $0.63\mathsf{\text{V}}$0.63V, zero drift will occur at $V_{GS}=0\mathsf{\text{V}}$VGS​=0V when $I_D=I_{DSS}$ID​=IDSS​.

Since $\mid V_{GS(OFF)}\mid$∣VGS(OFF)​∣ normally lies within the range $1.0\mathsf{\text{V}}<\mid V_{GS(OFF)}\mid <5.0\mathsf{\text{V}}$1.0V<∣VGS(OFF)​∣<5.0V we see from Equation 7 that the condition for zero temperature coefficient occurs when $V_{GS}$VGS​ is close to the gate-source cut-off voltage.

With the JFET operating at zero drift,

$$\begin{array}{cccc}& {\displaystyle I_{DZ}=I_{DSS}{\left(\frac{0.63}{V_{GS(OFF)}}\right)}^2}& & \end{array}$$IDZ​=IDSS​(VGS(OFF)​0.63​)2​(8)​

$$\begin{array}{cccc}& {\displaystyle g_{MZ}=g_{FS}^{\mathrm{\prime }}\left(\frac{0.63}{V_{GS(OFF)}}\right)}& & \end{array}$$gMZ​=gFS′​(VGS(OFF)​0.63​)​(9)​

Should the JFET under consideration for operation at zero temperature-coefficient have a high $V_{GS(OFF)}$VGS(OFF)​, its operating drain current $I_D$ID​ will be considerably less than its saturation drain current $I_{DSS}$IDSS​. Likewise, for most JFETs the resulting transconductance may be too low to be practical.

Operating at drain currents other than $I_{DZ}$IDZ​ will result in a drift in $V_{GS}^2$VGS2​,

$$\begin{array}{cccc}& {\displaystyle V_{GSDRIFT}=2.2\mathsf{\text{mV}}\mathsf{\text{/}}\mathsf{\text{°C}}(1-\sqrt{\frac{I_D}{I_{DZ}}})}& & \end{array}$$VGSDRIFT​=2.2mV / °C(1−IDZ​ID​​​)​(10)​

Conclusions

The values of $I_{DZ}$IDZ​ and $g_{MZ}$gMZ​ are proportional to the size of the JFET as defined by its geometry. For the 2N4117/A family we might anticipate an $I_{DZ}$IDZ​ of $40\text{–}50\mu \mathsf{\text{A}}$40–50μA, with an associated $g_{MZ}\mathsf{\text{of}}\mu \mathsf{\text{S}}$gMZ​ of μS; for the 2N4338 family an $I_{DZ}\mathsf{\text{of}}300\mu \mathsf{\text{A}}$IDZ​ of 300μA and a $g_{MZ}\mathsf{\text{of}}500\mu \mathsf{\text{S}}$gMZ​ of 500μS; and for the 2N4393 series an $I_{DZ}\mathsf{\text{closer}}\mathsf{\text{to}}3\mathsf{\text{mA}}\mathsf{\text{with}}\mathsf{\text{a}}{g}_{MZ}\mathsf{\text{in}}\mathsf{\text{the}}\mathsf{\text{area}}\mathsf{\text{of}}5\mathsf{\text{mS}}$IDZ​ closer to 3mA with a gMZ​ in the area of 5mS.

When operating a JFET below its zero-temperature coefficient, as the temperature rises both drain current and transconductance also rise. Above the JFET’s temperature-coefficient the opposite holds true.

1. Richard S. C. Cobbold, Theory and applications of Field-Effect Transistors, ©1970 John Wiley & Sons, §3.7.2 “Effects of Temperature on the Channel,” pp. 121-128.
2. Designing With Field-Effect Transistors, 2nd ed., revised by Ed Oxner, ©1990 McGraw-Hill, Inc.